The present invention relates to an analog MOS semiconductor device, such as an operational amplifier, a comparator, an analog switch, a sense amplifier for a memory, a low noise amplifier, or a mixer, including a MOS transistor, a capacitor, a resistor, an inductor, a diode, etc., and also relates to a method for manufacturing the same.
In recent years, along with the development in the system on chip technology, more and more LSIs including analog circuits and digital circuits integrated together have been developed each year. Accordingly, there is a demand for a significant reduction in the development time and the number of development steps and for improving the performance. There is also a demand for an automated layout process for an analog MOS semiconductor circuit.
A conventional analog MOS semiconductor device will now be described. FIG. 23 illustrates a circuit configuration of an operational amplifier as an analog MOS semiconductor device. The operational amplifier illustrated in the figure includes a P-channel transistor MP1 (21), a P-channel transistor MP2 (22), a P-channel transistor MP5 (25), a P-channel transistor MP6 (26), an N-channel transistor MN3 (23), an N-channel transistor MN4 (24), an N-channel transistor MN7 (27), a capacitor Cc (28), and a resistor Rc (29). The operational amplifier also includes a positive side input terminal V+ (30), a negative side input terminal Vxe2x88x92 (31), an output terminal Vo (32), a bias voltage input terminal VBIAS (33), a positive side power supply VDD (34), and a negative side power supply VSS (35).
Table 1 below shows the channel width W and the channel length L of each of the MOS transistors MP1 to MN7, the resistance value of the resistor Rc, and the capacitance value of the capacitor Cc of the operational amplifier of FIG. 23, as an example of the results of a design process.
FIG. 24 illustrates a conventional layout of the operational amplifier of FIG. 23. The size of each of the seven transistors MP1 (21) to MN7 (27) in FIG. 24 represents a layout area occupied by the transistor according to the channel width W and the channel length L thereof. This similarly applies to the capacitor Cc and the resistor Rc.
A condition for realizing systematic offset voltage SVoff=0 in a circuit design of an operational amplifier is shown by Expression (4.182) on page 210 in xe2x80x9cAnalog MOS Integrated Circuit For Signal Processingxe2x80x9d, R. Gregorian, G. C. Temes, John Wiley and Sons. Applying this expression to the operational amplifier of FIG. 23, the following expression needs to hold:
(W/L)MN3/(W/L)MN7
=(W/L)MN4/(W/L)MN7
=(W/L)MP5/(W/L)MP6/2xe2x80x83xe2x80x83(1)
The channel width W and the channel length L of the transistors are determined so as to satisfy Conditional Expression (1) above.
Furthermore, a condition for realizing random offset voltage RVoff=0 in a circuit design of an operational amplifier is shown by Expression (4.185) on page 211 in the same article. Applying the expression to the operational amplifier of FIG. 23, the following expression needs to hold:
(W/L)MP1=(W/L)MP2xe2x80x83xe2x80x83(2)
In the operational amplifier configuration, the P-channel transistor MP1 (21) and the P-channel transistor MP2 (22) are a pair of transistors that together form a differential input circuit.
Similarly, another condition for realizing random offset voltage RVoff=0 is shown by Expression (4.183) on page 211 in the same article. Applying the expression to the operational amplifier of FIG. 23, while taking into consideration the preconditions for the expression set forth in this article, the following expression needs to hold:
(W/L)MN3=(W/L)MN4xe2x80x83xe2x80x83(3)
In the operational amplifier configuration, the N-channel transistor MN3 (23) and the N-channel transistor MN4 (24) are a pair of transistors that together form a current mirror. The value of the capacitor Cc and the value of the resistor Rc are determined so that the phase margin of the operational amplifier is satisfied as described in the article.
However, even if the channel width W and the channel length L of the seven transistors MP1 (21) to MN7 (27) are designed so as to satisfy Conditional Expression (1) for realizing systematic offset voltage SVoff=0 as described above, the value of the channel width W of each transistor may be slightly shifted from the design value due to various process errors occurring in a semiconductor manufacturing process. As a result, seven transistors that are actually obtained as described above do not satisfy Conditional Expression (1) for realizing systematic offset voltage SVoff=0, whereby a systematic offset voltage SVoff occurs. A systematic uniform shift will now be described. This shift is shown in FIG. 25 with the P-channel transistor MP5 (25) as an example.
FIG. 25 shows, on the left side, an example of a layout of the P-channel transistor MP5 (25) using the design values described above. The transistor includes a gate 7 in the central position, and a source 6 and a drain 8 arranged on the opposite sides of the gate 7. The source 6 and the drain 8 are connected to aluminum wires 9 and 9 via contacts 10. Moreover, a P-type impurity diffusion region 11 is provided for forming a channel of a P-channel transistor, and the channel width W of the P-channel transistor MP5 (25) that is drawn on the left side of the figure is designed to be equal to the width of the P-type impurity diffusion region 11.
As an example, it is assumed that a uniform process error of xcex94W occurs in the decreasing direction in the semiconductor manufacturing process. FIG. 25 shows, on the right side, the manufactured P-channel transistor MP5 (25). The width of the P-type impurity diffusion region 11 of the P-channel transistor MP5 (25) that is drawn on the right side of the figure is reduced by xcex94W at each end, and thus the width is reduced by 2xcex94W in total. Therefore, the actual channel width W of the manufactured P-channel transistor MP5 (25) is expressed as follows:
(Wxe2x88x922xcex94W)MP5xe2x80x83xe2x80x83(4)
Similarly, the process error in the semiconductor manufacturing process occurs uniformly for other transistors of the operational amplifier illustrated in FIG. 23. Therefore, the actual channel widths W of the manufactured transistors are expressed as follows:
(Wxe2x88x922xcex94W)MN3xe2x80x83xe2x80x83(5)
(Wxe2x88x922xcex94W)MN4xe2x80x83xe2x80x83(6)
(Wxe2x88x922xcex94W)MP6xe2x80x83xe2x80x83(7)
(Wxe2x88x922xcex94W)MN7xe2x80x83xe2x80x83(8)
Therefore, substituting Expressions (3) to (8) into Expression (1) gives the following expression:
{(Wxe2x88x922xcex94W)/L}MN3/{(Wxe2x88x922xcex94W)/L}MN7
={(Wxe2x88x922xcex94W)/L}MN4/{(Wxe2x88x922xcex94W)/L}MN7
xe2x89xa0{(Wxe2x88x922xcex94W)/L}MP5/{(Wxe2x88x922xcex94W)/L}MP6/2xe2x80x83xe2x80x83(9)
Thus, the conditional expression for realizing systematic offset voltage SVoff=0 no longer holds. Therefore, the systematic offset voltage SVoff occurs due to various systematic process errors in the semiconductor manufacturing process.
On the other hand, the article, page 211, line 15 from the bottom to line 12 from the bottom, states that in the circuit configuration of an analog MOS semiconductor device, Conditional Expression (1) for realizing systematic offset voltage SVoff=0 can be satisfied as follows: xe2x80x9cIf ratios as large as (or larger than) two are required, then the wider transistor can be realized by the parallel connection of two (or more) xe2x80x9cunit transistorsxe2x80x9d of the size of the narrower onexe2x80x9d. Specifically, with a transistor (first transistor) having the minimum channel width W being a unit transistor, when a second transistor having a channel width kW (k is an integer) that is an integer multiple of the minimum channel width W is provided by the parallel connection of an integral number of unit transistors, even if a systematic process error occurs in each unit transistor, what occurs in the second transistor is an error that is an integer multiple of the process error, whereby the channel width of the second transistor remains to be an integer multiple of that of the first transistor, thus preventing the systematic offset voltage SVoff from occurring.
However, with a transistor of the minimum channel width W being used as a unit in an actual circuit design, it is only possible under the very rare condition xe2x80x9cIf ratios as large as (or larger than) two are requiredxe2x80x9d as stated in the article to provide each of the other transistors with a channel width W that is an integer multiple of the minimum channel width W.
Next, the influence of a random shift, rather than the systematic uniform shift as described above, will be described with reference to FIG. 26A and FIG. 26B using the pair of N-channel transistors MN3 (23) and MN4 (24) as an example.
FIG. 26A illustrates an example of a layout of the N-channel transistors MN3 (23) and MN4 (24) manufactured according to the design values shown in Table 1 above. Referring to FIG. 26A, an N-type impurity diffusion region 12 for forming a channel of an N-channel transistor is provided, and the channel width W of the transistors MN3 (23) and MN4 (24) is designed to be equal to the width of the N-type impurity diffusion region 12.
FIG. 26B illustrates an example of a layout of the pair of N-channel transistors MN3 (23) and MN4 (24) after the semiconductor manufacturing process, where a process error has occurred randomly in the semiconductor manufacturing process, thereby increasing only the channel width W of the transistor MN3 (23), among the pair of transistors, by xcex94W. Assuming that the width of the N-type impurity diffusion region 12 of the N-channel transistor MN3 (23) has increased by xcex94W at one end whereas the width of the N-type impurity diffusion region 12 of the N-channel transistor MN4 (24) has not increased or decreased, the actual channel widths W of the two manufactured N-channel transistors MN3 (23) and MN4 (24) are expressed as follows:
(W+xcex94W)MN3xe2x80x83xe2x80x83(10)
(W)MN4xe2x80x83xe2x80x83(11)
Therefore, substituting Expressions (10) and (11) into Conditional Expression (3) for realizing random offset voltage RVoff=0 gives the following expression:
{(W+xcex94W)/L}MN3xe2x89xa0(W/L)MN4xe2x80x83xe2x80x83(12)
Thus, the equation no longer holds, indicating that the random offset voltage RVoff occurs due to various random process errors in the semiconductor manufacturing process.
An object of the present invention is to provide an analog MOS semiconductor device in which even if a process error occurs in a semiconductor manufacturing process, the systematic offset voltage SVoff and the random offset voltage RVoff can be sufficiently suppressed.
In order to achieve the object, according to the present invention, the unit transistor is not a transistor having the smallest channel width, among a plurality of MOS transistors included in an analog MOS semiconductor device. Instead, a transistor having a channel width that is obtained by dividing the smallest channel width by an integer is used as a micro-unit transistor so that each of the plurality of MOS transistors includes a number of micro-unit transistors.
Specifically, an analog MOS semiconductor device of the present invention is an analog MOS semiconductor device, including a plurality of MOS transistors, wherein: a transistor having a channel width that is obtained by dividing, by an integer, a smallest channel width among those of the plurality of MOS transistors is used as a micro-unit transistor; and each of the plurality of MOS transistors includes a plurality of micro-unit transistors.
In one embodiment, the plurality of MOS transistors include two types of MOS transistors of P-type MOS transistors and N-type MOS transistors; and the micro-unit transistors include two types of micro-unit transistors of P-type micro-unit transistors and N-type micro-unit transistors.
In one embodiment, each of MOS transistors that are included in a conditional expression for realizing zero systematic offset voltage includes a number of micro-unit transistors that satisfies the conditional expression for realizing zero systematic offset voltage.
In one embodiment, the micro-unit transistors of each MOS transistor overlap with one another.
In one embodiment, each micro-unit transistor includes an even number of small transistors; the even number of small transistors are connected in parallel to one another; and two of the even number of small transistors connected in parallel to one another that are located at opposite ends each have a source located at one end of the micro-unit transistor.
In one embodiment, the micro-unit transistor is a pair transistor including two small transistors connected in parallel to each other; and a source of one of the small transistors is located at one end of the pair transistor, and a source of the other one of the small transistors is located at the other end of the pair transistor.
In one embodiment, the micro-unit transistor includes a substrate contact via which one or more of electrodes of the micro-unit transistor is connected to a semiconductor substrate.
In one embodiment, the micro-unit transistor includes a gate contact connected to a gate of the micro-unit transistor, and a gate wire connected to the gate contact for applying a gate voltage to the gate.
In one embodiment, dummy micro-unit transistors are provided for adjusting a power of one or more of the plurality of MOS transistors.
In one embodiment, the dummy micro-unit transistors include two types of dummy micro-unit transistors of P-type dummy micro-unit transistors and N-type dummy micro-unit transistors.
In one embodiment, two MOS transistors forming a pair, among the plurality of MOS transistors, each include a number of micro-unit transistors that is a multiple of four.
In one embodiment, the plurality of MOS transistors have an SOI structure or an SOS structure.
A method for manufacturing an analog MOS semiconductor device of the present invention is a method for manufacturing an analog MOS semiconductor device including a plurality of MOS transistors, including the steps of: preparing a plurality of micro-unit transistors each having a channel width that is obtained by dividing, by an integer, a smallest channel width among those of the plurality of MOS transistors; and manufacturing the plurality of MOS transistors using the plurality of micro-unit transistors so that each of the plurality of MOS transistors includes more than one of the micro-unit transistors.
In one embodiment, if the plurality of MOS transistors include two types of MOS transistors of P-type MOS transistors and N-type MOS transistors, two types of micro-unit transistors of P-type micro-unit transistors and N-type micro-unit transistors are prepared as the micro-unit transistors, so that each P-type MOS transistor includes more than one of the P-type micro-unit transistors and each N-type MOS transistor includes more than one of the N-type micro-unit transistors.
In one embodiment, when manufacturing MOS transistors that are included in a conditional expression for realizing zero systematic offset voltage, the number of micro-unit transistors to be included in each of the MOS transistors is set to be a number that satisfies the conditional expression for realizing zero systematic offset voltage.
A program for manufacturing an analog MOS semiconductor device of the present invention is a program for manufacturing an analog MOS semiconductor device including a plurality of MOS transistors, the program including the steps of: defining, as a micro-unit transistor, a transistor having a channel width that is obtained by dividing, by an integer, a smallest channel width among those of the plurality of MOS transistors; and designing the plurality of MOS transistors so that each of the plurality of MOS transistors includes a plurality of micro-unit transistors.
A program device of the present invention is a program device, including the manufacturing program as described above, wherein the program device has an EDA function or a CAD function for manufacturing an analog MOS semiconductor device including a plurality of MOS transistors based on the manufacturing program.
As described above, according to the present invention, a micro-unit transistor is used as a unit, and each MOS transistor includes a plurality of micro-unit transistors. Therefore, even if the channel width ratio among a plurality of MOS transistors is not an integer ratio, it is possible to sufficiently suppress the occurrence of the systematic offset voltage SVoff when a systematic process error occurs.
Particularly, according to the present invention, a plurality of micro-unit transistors are arranged in a layout in which they overlap with one another. Therefore, it is possible to reduce the layout area of each MOS transistor while satisfying the condition for realizing systematic offset voltage SVoff=0.
Moreover, according to the present invention, each micro-unit transistor includes an even number of small transistors connected in parallel to one other, wherein sources of two small transistors that are located at opposite ends are located at opposite ends of the micro-unit transistor. Therefore, when a substrate contact is provided around the micro-unit transistor so as to be connected to the sources, the sources of the small transistors and the substrate contact are located close to each other, thereby shortening the distance therebetween and thus reducing the layout area. Furthermore, since the even number of small transistors can share a drain, the drain area is reduced and thus the capacitance component that is parasitic on the drain is reduced, thereby increasing the operation speed of the micro-unit transistor.
Furthermore, according to the present invention, when each MOS transistor includes a plurality of micro-unit transistors, the plurality of micro-unit transistors each have a substrate contact, whereby the potential of the substrate of the MOS transistor is stably maintained at the same value irrespective of the position in the substrate, thus reducing the possibility for a latch-up phenomenon to occur.
In addition, according to the present invention, where a MOS transistor having a large channel width includes a number of micro-unit transistors, a gate voltage is individually applied to the gate of each of the number of micro-unit transistors via a corresponding gate wire. Therefore, a predetermined gate voltage is applied to the MOS transistor as a whole, whereby it is possible to obtain a driving power that is substantially equal to the design value.
Furthermore, according to the present invention, dummy micro-unit transistors are provided for adjusting the power of the MOS transistor. Therefore, a fine adjustment of the channel width of the MOS transistor can be made by connecting one or more of the dummy micro-unit transistors by modifying the wiring structure. Thus, it is possible to reduce the development time for an analog MOS semiconductor device by reducing the amount of time required for making prototypes.
Moreover, according to the present invention, each of two MOS transistors forming a pair includes a number of micro-unit transistors that is a multiple of four, whereby it is possible to arrange the pair of MOS transistors in a centroid structure. Therefore, it is possible to more effectively suppress the systematic offset voltage.
Furthermore, according to the present invention, a plurality of MOS transistors have an SOI structure or an SOS structure, whereby it is possible to realize an operation under an extremely low voltage and to reduce the influence of shot noise due to radioactive rays such as xcex1 rays. Furthermore, in an analog/digital mixed semiconductor device, it is possible to effectively reduce the influence of noise creeping into the analog section from the digital section.
In addition, according to the present invention, a circuit design process for a plurality of MOS transistors each including a plurality of micro-unit transistors can be automated, thereby effectively reducing the design/development time for an analog MOS semiconductor device and effectively reducing the development cost therefor.